A non-overlapping clock

September 5, 2012 3:37:56 AM CDT

I'm planning to build some switched-capacitor circuits, and one of the basic requirements for that is a non-overlapping clock.

A basic switched capacitor circuit looks like this:

A switched 
capacitor shunt

The switch to the left closes, charging the capacitor:

Charging the 

then the switch on the right closes, discharging the cap:

Discharging the 

Thing is, you never want both switches to be closed at the same time:

Just.. don't

That condition is called called 'shoot-through', and Can Be Bad. At best it will hurt your circuit's accuracy and efficiency, and at worst it can short-circuit parts of your circuit that were never supposed to meet.

The way to avoid shoot-through is simple: make sure there's a period when both switches are open before either switch can close.

You generally do that with the signals that control the switches rather than with the switches themselves. First, it's easier to generate control signals that do the right thing than to build switches that can compensate for a control signal that could cause trouble. Second, most switched-capacitor circuits use more than two switches, so it makes sense to solve the problem once and use the solution many times.

Making a non-overlapping clock:

From what I've seen in the literature, there are two basic ways to make a non-overlapping clock.

The first uses simple logic and a pair of short delay lines:


The NAND gates guarantee mutual exclusion. A NAND gate's output goes LOW when both its inputs are high. You have to walk through the logic tables to prove it, but there's no possible combination of inputs that allows two cross-connected NAND gates to have LOW output at the same time.

The four inverters to the right are delay buffers. The inversion of an inversion is the same as the original signal, so the output from the second inverter is the same as the output from the NAND gate two steps back. It takes each inverter a little while to change state though (it's called 'propagation delay'), so there's a delay between one NAND gate's output changing and the other NAND gate seeing the new value as input.

The inverter to the lower left is the final piece of the machine. Again, you have to go through the logic tables to prove it, but if two cross-coupled NAND gates see opposite values on their other input, the circuit will only be happy if the NAND gates see the same value at both inputs.

When you combine mutual exclusion, the requirement for both inputs at each gate to be equal, and a delay while the circuit settles into a state that's stable, you get a circuit whose outputs will never be HIGH at the same time.

Technically, you could take output from any point along the delay line, but taking it from the center of the delay buffer gives you one inverter's worth of isolation between the output signal and any part of a NAND gate.

The second kind of circuit uses a long delay line and more complex logic:

delay-line-based NOC

By combining the input clock signal with the signals at various points on the delay line, you can get a whole range of waveforms that turn on and off in carefully-defined sequences.

Things like microprocessors and microcontrollers use the delay-line version because CPU timing is a delicate art. For the circuits I plan to build, the simple two-phase version will be good enough.

Enough theory.. let's make stuff

Here's a working version of the circuit, built using my new favorite breadboarding technique:

Oblique view of the circuit

The chip plugged into the breadboard is a 74HC14 hex Schmitt trigger inverter. Four of the inverters are connected for the delay lines, and one is set up as a pulse generator.

The chip on the breakout board to the lower left is a 74HC00 quad NAND gate. Only two of the gates are in use, and the wires for the others are floating (literally) plugged into the 1x3 female headers to keep them from getting snarled up and in the way.

The chip on the breakout to the upper right is a 74LVC74 dual D-type flip flop, only one side of which is in use. That's set up as a divide-by-two circuit, with the input connected to the inverting output.

Pulses from the '14's pulse generator go to the 74's clock pin, telling it to copy and hold whatever value it sees at its input. Since the input is tied to the inverting output, the output changes with every pulse. The result is a square wave whose frequency is half that of the '14's pulse train.

I chose to use the flip flop for two reasons:

First, it's easier to make a Schmitt trigger relaxation oscillator work as a pulse generator than to get a true 50%-duty-cycle square wave out of it. All we're really doing is chopping the LOW pulse down to a couple of microseconds, and leaving the HIGH pulse as it was. One RC timing curve is easier to keep stable than two.

Second, the '74 has complementary outputs.. you get the input value on one pin and the opposite value on another pin. We need complementary inputs for the logic circuitry anyway, and this is a convenient way to get it.

Here's another view that makes it a little easier to see all the connections:

A view showing how the inputs 
cross over

The white wires coming away from the '00 are the inputs that receive the complementary clock signals, the yellow lines are the ones that receive input from the delay buffers. The blue lines are the outputs that drive the delay buffers.

The yellow line leading to the '74 is the clock input, which connects to the pulse generator. The blue lines are outputs that go to the '00's white input lines, the white wire is the '74's input line (connected to the complementary output through a resistor) and the black lines are the SET and RESET pins, which are connected to Vcc to keep them from causing trouble.

You can't see much detail of the pulse generator itself, but the capacitor to the upper right is the timing cap. One leg is connected to GND, the other to the inverter's input. There's a resistor from Vcc to the inverter's input that charges the cap, and a diode between the inverter's input and output that discharges the cap quickly when the inverter goes LOW.

So, does it work?

Yes.. yes it does:

The output waveforms - 2v x 
50us scale

The voltage scale is 2v per division and the time scale is 50uS per division. What you're seeing is a pair of opposing square waves with a period of about 12 kilohertz.

The widened/doubled vertical lines moving out from the center show jitter in the clock, most likely from variations in the pulse train. That's hardly surprising, as the three-component circuit I built is about as quick and dirty as you can get.

That's nice, but is it truly non-overlapping?

As a matter of fact, it is.

Here are traces for the rising and falling edges of the pulses. The vertical scale is still 2v/div, but the time scale is now 50 nanoseconds per division:

Rising edge - 2v x 50ns 
scale Falling edge - 2v x 
50ns scale

The blue trace is cleaner than the yellow one, showing an almost-perfect critically damped curve at its rising edge (first photo). There's some noise at the low side (probably because I didn't put decoupling caps on all the chips) but the levels are tolerable for a "let's see if this works" build.

The yellow trace rings for about 100 nanoseconds after reaching its new voltage level, which I'll blame on parasitic capacitance in the breadboard unless I can think of a better excuse. Given that the ringing fills about . 2% of the overall waveform, I'll live with it for now.

In both cases, there's clearly a notch where both signals are low before either trace rises. In the upper photo it's about 10 nanoseconds, in the lower one it's about 25 nanoseconds.

Both the noise and the ringing can be solved by tidier circuit construction and a bit of resistance between the logic stages. If I want to increase the delay, I can do it by throwing some more resistance and capacitance between the inverters.


Overall, this was a successful proof of concept.

The circuit isn't perfect as it stands, but I don't expect perfection from anything that contains a breadboard and a rat's nest of wires.

The basic design clearly works, and I know how to solve all the problems immediately visible in the output. The next step will be to build a more disciplined version of the circuit, and tune that until I get the performance I want.

In the meantime, I'll have to figure out what I can make using the one inverter, one flip flop, and two NAND gates still sitting free.

Random brain cookies:

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